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Application Note 9822
Appendix D HI5767 Theory of Operation
The HI5767 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 16 depicts
the circuit for the front end differential-in-differential-out
sample-and-hold (S/H). The switches are controlled by an
internal sampling clock which is a non-overlapping two phase
signal , Φ 1 and Φ 2 , derived from the master sampling clock.
During the sampling phase, Φ 1 , the input signal is applied to
the sampling capacitors, C S . At the same time the holding
capacitors, C H , are discharged to analog ground. At the
falling edge of Φ 1 the input signal is sampled on the bottom
plates of the sampling capacitors. In the next clock phase, Φ 2 ,
the two bottom plates of the sampling capacitors are
connected together and the holding capacitors are switched to
the op-amp output nodes. The charge then redistributes
between C S and C H completing one sample-and-hold cycle.
The front end sample-and-hold output is a fully-differential,
sampled-data representation of the analog input. The circuit
not only performs the sample-and-hold function but will also
convert a single-ended input to a fully-differential output for
the converter core. During the sampling phase, the V IN pins
see only the on-resistance of a switch and C S . The relatively
small values of these components result in a typical full power
input bandwidth of 250MHz for the converter.
As illustrated in the functional block diagram, Figure 17, eight
identical pipeline subconverter stages, each containing a two-
bit flash converter and a two-bit multiplying digital-to-analog
converter, follow the S/H circuit with the ninth stage being a two
bit flash converter. Each converter stage in the pipeline will be
sampling in one phase and amplifying in the other clock phase.
Each individual subconverter clock signal is offset by 180
degrees from the previous stage clock signal resulting in
alternate stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit
subconverter stages is a two-bit digital word containing a
supplementary bit to be used by the digital error correction
logic. The output of each subconverter stage is input to a
digital delay line which is controlled by the internal
sampling clock. The function of the digital delay line is to
time align the digital outputs of the eight identical two-bit
subconverter stages with the corresponding output of the
ninth stage flash converter before applying the eighteen bit
result to the digital error correction logic. The digital error
buffered latching technique. The digital output data is
available in two’s complement or offset binary format
depending on the state of the Data Format Select (DFS)
control input.
Internal Reference Voltage Output, V REFOUT
The HI5767 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. V REFOUT must be connected to V REFIN when
using the internal reference voltage.
An internal bandgap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference
voltage used by the converter. A 4:1 array of substrate
PNPs generates the “delta-V BE ” and a two-stage op amp
closes the loop to create an internal +1.25V bandgap
reference voltage. This voltage is then amplified by a wide-
band uncompensated operational amplifier connected in a
gain-of-two configuration. An external, user-supplied,
0.1 μ F capacitor connected from the V REFOUT output pin to
analog ground is used to set the dominant pole and to
maintain the stability of the operational amplifier.
Reference Voltage Input, V REFIN
The HI5767 is designed to accept a +2.5V reference voltage
source at the V REFIN input pin. Typical operation of the
converter requires V REFIN to be set at +2.5V. The HI5767 is
tested with V REFIN connected to V REFOUT yielding a fully
differential analog input voltage range of ± 0.5V.
The user does have the option of supplying an external
+2.5V reference voltage. As a result of the high input
impedance presented at the V REFIN input pin, 2.5k ?
typically, the external reference voltage being used is only
required to source 1mA of reference input current. In the
situation where an external reference voltage will be used
an external 0.1 μ F capacitor must be connected from the
V REFOUT output pin to analog ground in order to maintain
the stability of the internal operational amplifier.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V REFIN .
.
correction logic uses the supplementary bits to correct any
error that may exist before generating the final ten bit digital
data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 7th cycle of the clock after the
analog sample is taken. This time delay is specified as the
data latency. After the data latency time, the digital data
V IN +
V IN -
Φ 1
Φ 2
Φ 1
C S
C S
Φ 1
Φ 1
-
+
C H
C H
Φ 1
Φ 1
V OUT +
V OUT -
representing each succeeding analog sample is output
during the following clock cycle. The digital output data is
synchronized to the external sampling clock by a double
3-13
FIGURE 16. ANALOG INPUT SAMPLE-AND-HOLD
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